Incrementers, decrementers and prioritizers which are based on half adder type of logic are widely used in the design of microprocessors, microcontrollers and other digital control systems. These elements based on `ripple carry` consume fewer gates and cost less area but can involve large amounts of propagation delays. Fast carry look-ahead logic has been incorporated into these elements in applications which demand lesser propagation delays or faster operation. The look-ahead logic propagates the carry input signal of a stage to the carry output of the stage when all the primary data inputs of the stage are `HIGH` for the incrementer and all the primary data inputs of that stage are `LOW` for the decrementer. Since the propagation delay through the look-ahead carry signal is independent of the ripple delay within the stages the entire circuit operates faster.
An example of currently used look-ahead carry logic is shown in FIG. 1 where the look-ahead carry logic for each stage consists of a `n` input distributed NAND gate for a `n` bit wide stage (the example in FIG. 1 is a four bit stage), two inverters and an AND-OR-INVERT circuit. Thus the carry look-ahead circuit of FIG. 1 is comprised of Inverter 100, AND-OR-INVERT circuit (AND gate 102, NOR gate 106, AND gate 108), Inverter 104, and NAND gate 110. There is a need for a new circuit and method to compute the carry which involves less propagation delay and uses fewer gates and hence facilitates a more competitive integrated circuit or system design. It is a technical advantage of this invention to improve the look-ahead carry signal for half adder type of elements using a fewer number of transistors and hence fewer gate delays.
Further technical advantages of the invention will become apparent to those of ordinary skill in the art having reference to the following specification, together with its drawings.